IWLS 2005 Benchmarks

logic

New benchmarks collected, synthesized and released in June 2005:

84 designs with up to 185,000 registers and 900,000 gates collected from different websites.
All designs mapped with Cadence RTL Compiler in a quick synthesis run to a 180 nm library.
Available in two formats, in Verilog and in OpenAccess.

Initiated by Christoph Albrecht, Cadence Research Laboratories at Berkeley.

Download

RTL-source files and the mapped netlists in Verilog and OpenAccess (compressed tar-file, 213.3 MB)

Presentation given at the IWLS workshop in June 2005 (pdf-file)

ISCAS