| Friday May 29 |
| 14:00–19:00: Registration & Reception |
Lobby @ Marco Polo Hongkong Hotel |
| Saturday May 30 |
| 09:00–09:10: Opening session |
Opening |
| 09:10–10:10: Keynote |
Keynote 1 (Chair: Wei Zhang) |
| |
AI-Hardware Co-Design: Advancing Quality, Productivity, and Reliability |
Deming Chen (University of Illinois at Urbana-Champaign, USA) |
| 10:10–10:50: Paper session |
Synthesis for FPGA (Chair: Heinz Riener) |
| 29 |
Frontier-Based Joint Covering for Dual-Output LUT Mapping (Best student paper candidate) |
Yaojia Wang, Hongyang Pan and Keren Zhu |
| 13 |
MFFW-Based Refactoring for LUT Networks |
Chengyu Ma, Yinshui Xia, Lunyao Wang and Zhufei Chu |
| 10:50–11:10: Coffee break |
|
| 11:10–12:30: Paper session |
Logic Synthesis for Specialized Targets (Chair: Marcel Walter) |
| 12 |
GLOW: Glitch Optimization with Retiming for Low Power (Best student paper candidate) |
Jiantao Liu, Carmine Rizzi, Pravriti Jaipuriyar, Ulrike Schorr, Sascha Richter, Ankush Sood and Lana Josipovic |
| 2 |
Pattern-Guided Local Architecture–Synthesis Exploration for Arithmetic Datapaths |
Ruofei Tang, Yiwen Wang, Xing Li, Jiaping Tang, Lei Chen, Huawei Li, Mingxuan Yuan and Jianliang Xu |
| 5 |
Quality-Driven Approximate Logic Synthesis via Library-Based Subcircuit Rewriting |
Wenhui Liang, Ruicheng Dai and Weikang Qian |
| 7 |
Single-Rail Cascades for Symmetric Functions |
Tsutomu Sasao and Alan Mishchenko |
| 12:30–14:00: Lunch |
|
| 14:00–15:30: Panel discussion |
Front-End EDA Agents: Who Owns the Intelligence, Who Signs Off, and What Should Be Standardized? |
| |
Moderator:
Qiang Xu, CUHK / X-EPIC |
Panelists:
Giovanni De Micheli, EPFL
Ankush Sood, Cadence
Fengbin Tu, HKUST
Yun Shao, Giga-da
Xi Wang, Southeast University / ChipEvo Intelligence |
| 15:30–15:40: Poster session |
Poster Session (Chair: Min Li) |
| 15 |
Mapping-Aware Resubstitution via Functional Reconstruction |
Yanzhen Wang, Chen Lv, Yinshui Xia, Lunyao Wang and Zhufei Chu |
| 18 |
FAO: A Functionality-Aware Logic Synthesis Framework |
Shourui Ji, Mingxiao He, Xinyi Luo, Pengcheng Huang and Zhenyu Zhao |
| 15:40–16:10: Poster & coffee break |
|
| 16:10–17:10: Paper session |
Core Logic Optimization and Representation Techniques (Chair: Zhiang Wang) |
| 10 |
Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation |
Jingren Wang, Guangyu Hu, Shiju Lin and Hongce Zhang |
| 14 |
VeLoR: Verification-Oriented Logic Representation and Parallel Solving for Combinational Equivalence Checking |
Zhang Hu, Yinshui Xia, Lunyao Wang and Zhufei Chu |
| 21 |
A Framework for Post-Mapping Feedback-Guided Selective Logic Transformations |
Michael Feldmeier, Marcel Walter and Robert Wille |
| 17:10–17:25: Benchmark session |
|
| Sunday May 31 |
| 09:00–10:00: Keynote |
Keynote 2 (Chair: Zhufei Chu) |
| |
Logic Synthesis at Scale and Speed |
Evangeline F.Y. Young (The Chinese University of Hong Kong, China) |
| 10:00–10:40: Paper session |
Logic Synthesis for Emerging Technology (Chair: Gengjie Chen) |
| 4 |
FeSyn: BDD-based Logic Synthesis Approach Utilizing Ferroelectric Field-Effect Transistor Multiplexer |
Qianhuo Wu, Xiunan Sun, Lunyao Wang and Zhufei Chu |
| 28 |
Post-Mapping Optimization Method for RSFQ Circuits Based on Path Balancing |
Yitian Fei, Chengyu Ma, Yinshui Xia, Lunyao Wang and Zhufei Chu |
| 10:40–11:10: Coffee break |
|
| 11:10–12:30: Paper session |
Machine Learning for Logic Synthesis (Chair: Keren Zhu) |
| 6 |
Efficient Hybrid-action Search with QoR Prediction for Logic Synthesis Sequence Optimization (Best student paper candidate) |
Yunfei Dai, Mingyang Chen, Kaixiang Zhu, Yuanqi Wang, Qing He, Yu He and Lingli Wang |
| 16 |
Boolean Circuit Embedding under Equivalence Contrastive Constraints for Functionality Reasoning |
Xudong Hu, Yusen Mo and Min Li |
| 20 |
AIG2PT: A Generative Pre-trained Transformer for Unconditional And-Inverter Graph Synthesis |
Isabella Venancia Gardner, Marcel Walter, Robert Wille and Michael Cochez |
| 22 |
aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis |
Marcel Walter, Isabella Venancia Gardner and Robert Wille |
| 12:30–14:00: Lunch |
|
| 14:00–15:00: Paper session |
RTL Synthesis (Chair: Hongce Zhang) |
| 9 |
Enhancing RTL Synthesis through Extended E-Graph Architectures and Functional Operators |
Yang Sun, Chengxi Li, Lei Chen, Yiwen Wang, Mingxuan Yuan and Evangeline Young |
| 11 |
ParaYosys: Tail-Aware Partition-Based Parallel RTL Synthesis |
Zhengyi Zhang, Sijing Yang and Lingli Wang |
| 26 |
RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits |
Felix Arnold, Ryan Amaudruz, Renzo Andri, Lukas Cavigelli and Dimitrios Tsaras |
| 15:00–15:30: Contest |
Programming Contest Award (Attila Jurecska) |
| 15:30–16:00: Coffee break |
|
| 16:00–17:00: Paper session |
Advanced Technology Mapping Methods (Chair: Rongliang Fu) |
| 8 |
GNN-based Path-aware multi-view Circuit Learning for Technology Mapping |
Wentao Jiang and Zhufei Chu |
| 25 |
Subclass Technology Mapping with Supergates |
Joshua Russell and Hava Siegelmann |
| 27 |
YOCO: You Only Cut Once for Technology Mapping |
Xin Ning, Ruogu Ding, Ulf Schlichtmann and Weikang Qian |
| 17:00–17:20: Closing session |
Closing Session & Best Paper Award |
| Monday June 1 |
| Social Event |
Hiking Tour at Victoria Peak |
