Wednesday, June 8 11:45 - 1:00 : Lunch 1:15 - 2:35 : Sequential Synthesis chair: Tiziano Villa Do We Waste Logic on Circuit Initialization? N. Kitchen and A. Kuehlmann Retiming and Resynthesis: A Complexity Perspective J.-H. Jiang and R. Brayton High-Level Optimization by Combining Retiming and Shannon Decomposition C. Soviani, O. Tardieu, and S. Edwards Layout-driven Control Re-synthesis Using Re-encoding for Timing Closure C.-Y. Yeh and M. Marek-Sadowska 2:35 - 3:20 : Poster Session 1 Symmetrical, Dual and Linear Functions and Their Autocorrelation Coefficients J. Rice and R. Jansen High Throughput and Small Size Viterbi Decoder by Hybrid CMOS - Pseudo NMOS ACS Units A. Jahanian, B. Yen, P. Tomson, and M. Perkowski Making a Choice Between FDDs and BDDs: A Preliminary Investigation J. Rice Modeling and Synthesis of a Conventional Floating Point Fused Multiply-Add Arithmetic Unit Using CAD Tools J. Alghazo Multi-threaded Reachability D. Sahoo, J. Jain, S. Iyer, D. Dill, and E.A. Emerson Separating Retiming from the Initial States A. Ayupov, M. Kishinevsky, and A. Marchenko Finding Common Double-Vertex Dominators in Circuit Graphs M. Teslenko and E. Dubrova Functional Decomposition Using Algebraic Kernel K. Shinozuka A New Approach to the Use of Satisfiability in False Path Detection F. Marques, R. Ribas, S. Sapatnekar, and A. Reis Synthesis of Reversible Circuits A. De Vos and Y. Van Rentergem Framework for Improved Partitioning and Automatic Task Graph Extraction for State-Based Designs L. Demoracski and D. Avresky Memory-based Cross-talk Canceling CODECs for On-chip Buses C. Duan, K. Gulati, and S. Khatri Simultaneous Optimization of Delay and Number of Operations in Multiplierless Implementation of Linear Systems A. Hosangadi, F. Fallah, and R. Kastner Construction of Planar BDDs by Using Linearization and Decomposition I. Levin, R. Stankovic, M. Karpovsky, and J. Astola Robust Synthesis of Asynchronous Burst-Mode Machines G. Gill and M. Singh 3:20 - 5:00 : Logic Synthesis chair: Sunil Khatri Synthesis Methodology for Built-In At-Speed Testing Y. Li, A. Kondratyev, and R. Brayton Don't-care Computation Using k-clause Approximation K. McMillan Simulation and Satisfiability in Logic Synthesis J. Zhang, S. Sinha, A. Mishchenko, R. Brayton, and M. Chrzanowska-Jeske How Hard is Two-Level Logic Minimization: An Addendum to Garey & Johnson C. Umans, T. Villa, and A. Sangiovanni-Vincentelli Integrating Logic Synthesis, Technology Mapping, and Retiming A. Mishchenko, S. Chatterjee, J.-H. Jiang, and R. Brayton 5:10 - 6:10 : Power, Reliability and Fault Tolerance chair: Diana Marculescu A Code Placement Technique for Improving the Performance of Processors with Defective Caches T. Ishihara and F. Fallah Kauffman Networks: From Nature to Electronics E. Dubrova and M. Teslenko Techniques for Fault Reduction in Out-of-Order Microprocessors B. Gojman, V. Stojanovic, R.I. Bahar, and R. Weiss 6:10 - 6:30 : IWLS Benchmark Effort chair: Christoph Albrecht 6:30 - 8:00 : Dinner Thursday, June 9 7:30 - 8:30 : Breakfast 8:30 - 9:50 : Novel Applications of Decision Diagrams chair: Igor Markov Efficient Synthesis of Quantum Logic Circuits by Rotation-based Quantum Operators and Unitary Functional Bi-decomposition A. Abdollahi and M. Pedram Circuit Reliability Analysis Using Symbolic Techniques N. Miskov-Zivanov and D. Marculescu An Efficient Graph Based Representation of Circuits and Calculation of Their Coefficients in Finite Field A. Jabir and D. Pradhan A New Algorithm for Partitioned Model Checking S. Iyer, E.A. Emerson, D. Sahoo, and J. Jain 9:50 - 10:35 : Poster Session 2 Galois Switching Theory: A Uniform Framework for Multi-Level Verification D. Pradhan, A. Singh, T. Rajaprabhu, and A. Jabir Efficient Post-Layout Power-Delay Curve Generation M. Vujkovic, D. Wadkins, and C. Sechen Analytical Modeling and Reduction of Direct Tunneling Current During Behavioral Synthesis of Nanometer CMOS Circuits S. Mohanty, V. Mukherjee, and R. Velagapudi An Improved Approach for Alternative Wires Identification Y.-C. Chen and C.-Y. Wang Exact Lower Bound for the Number of Switches in Series to Implement a Combinational Logic Cell F. Schneider, R. Ribas, S. Sapatnekar, and A. Reis Predictive Reachability Using a Sample-based Approach D. Sahoo, J. Jain, S. Iyer, D. Dill, and E.A. Emerson Optimization Protocol Based on Low Power Metrics A. Verle, A. Landrault, P. Maurine, and N. Azemard GUIDO: Hybrid Verification Through Distance-Guided Simulation S. Shyam and V. Bertacco Efficient Stochastic Pruning for Variability-Driven Dual-Vth Leakage Optimization A. Davoodi and A. Srivastava Boolean Operations on Decomposed Functions S. Plaza and V. Bertacco A General Framework for Accurate Statistical Timing Analysis Considering Correlations V. Khandelwal and A. Srivastava Challenges in Synthesizing Fast Control-Dominated Circuits C. Soviani and S. Edwards On the Exact Minimization of Path-Related Objective Functions for BDDs R. Ebendt and R. Drechsler A Scheduling Method for Asynchronous Bundled-Data Implementations H. Saito, N. Jindapetch, T. Yoneda, and C. Myers An Efficient Jitter- and Skew-aware Methodology for Clock Tree Synthesis and Analysis V. Wason, R. Murgai, and W. Walker Equivalence Checking for Transformations and Optimizations in C Programs on Dependence Graphs T. Matsumoto, H. Saito, and M. Fujita 10:35 - 12:35 : Invited Session: Designing Secure Embedded Systems: Challenges & Opportunities for EDA chair: Mukul Prasad Challenges for the Logic Design of Secure Embedded Systems Patrick Schaumont Secure Embedded System Design: A Tale of Three Gaps Anand Raghunathan 12:35 - 1:35 : Lunch 2:00 - 6:00 : Hiking trip near Lake Arrowhead 6:30 - 8:00 : Dinner Friday, June 10 7:30 - 8:30 : Breakfast 8:30 - 9:50 : Technology Mapping chair: Victor Kravets Constructive Logic and Layout Synthesis Does Not Work Y. Oh, E. Ernst, K. Sakallah, and I. Markov Reducing Structural Bias in Technology Mapping S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam An Integrated Technology Mapping Environment A. Mishchenko, S. Chatterjee, R. Brayton, and M. Ciesielski Building a Better Boolean Matcher and Symmetry Detector D. Chai and A. Kuehlmann 9:50 - 10:35 : Poster Session: For first 16 presentations (through Thursday morning) 10:35 - 11:55 : Reconfigurable Logic chair: Mike Hutton FPGA Architecture Evaluation and Technology Mapping Using Boolean Satisfiability A. Ling, D. Singh, V. Manohararajah, and S. Brown Data Partitioning for Reconfigurable Architectures With Distributed Block RAM W. Gong, G. Wang, and R. Kastner Timing Driven Functional Decomposition for FPGAs V. Manohararajah, D. Singh, and S. Brown Factorizing Multiplexers in the Datapath to Reduce Cost in FPGAs D. Nancekievill and P. Matzgen 12:00 - 1:00 : Lunch 1:15 - 2:35 : Issues in High-Level Synthesis chair: Timothy Kam Physically Aware Data Communication Optimization for Hardware Synthesis R. Kastner, W. Gong, X. Hao, F. Brewer, A. Kaplan, P. Brisk, and M. Sarrafzadeh HLS Support for Unconstrained Memory Accesses G. Venkataramani, T. Chelcea, and S. Goldstein Polynomial-Time Graph Coloring Register Allocation P. Brisk, F. Dabiri, J. Macbeth, and M. Sarrafzadeh Analysis and Synthesis of Weighted-Sum Functions T. Sasao 2:35 - 3:15 : Poster Session: For last 17 presentations (all Friday presentations) 3:15 - 4:55 : Physical Design and Timing Analysis chair: Elena Dubrova Selective Application of Synthesis Transforms for Improved Computational Efficiency R. Hentschke, J. Narasimhan, and D. Kung Post-Placement Rewiring by Exhaustive Search for Functional Symmetries K.-H. Chang, I. Markov, and V. Bertacco Gate Sizing Using Incremental Parameterized Statistical Timing Analysis M. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov Computing Clock Skew Schedules Under Normal Process Variation A. Hurst and R. Brayton Variability Driven Buffer Insertion Considering Correlations A. Davoodi and A. Srivastava